As applications of embedded processors become more complex, the size of code for such applications is increasing, thereby increasing the size of processor code memory. However, increasing the size of the processor code memory is expensive and is also an inefficient use of chip real estate.
Some processors solve this problem by using a cache in place of the code memory. The cache stores only a portion of the code for an application at any given time. When the code address points to a code that is not in the cache at any particular point of time, a cache miss occurs. When a cache miss occurs, the new code is fetched into the code memory from system memory (such as DRAM). The new code replaces some of the existing and in most cases, the Least Recently Used (LRU) code.
Caching portions of the application code is expensive because special hardware is required for detecting cache misses, for translating cache misses into correct system memory accesses, and for deciding which code to replace.
Another possible solution would be to keep the processor under reset during the time new code is loaded into the code memory. However, resetting the processor erases all the information stored in the general purpose registers within the processor. Accordingly, a swap routine is used to copy the registers to the DRAM prior to a reset. The foregoing is disadvantageous because the swap routine resides in and consumes a significant amount of the code memory. In addition to the code space, time is also spent for swapping.